There is a relentless effort to make electronics and memory circuits smaller, which continues to drive semiconductor manufacturers. The industry is currently developing 3D integrated circuits (3DICs), which requires physically stacking integrated circuit chips and using Through Silicon Vias (TSV) filled with a conductor to electrically connect the chips. The 3DICs create new possibilities for miniaturization and circuit architectures. There are a variety of techniques and technologies required to facilitate 3DICs and the construction of TSVs. A hole utilized for a TSV is typically 5 to 100 microns in diameter and typically 50 to 500 microns deep. These etched features, and others such as trenches, are called High Aspect Ratio features because they have a greater depth than width. The generic construction process for 3DIC's is:                1) etch the TSV and fill with copper to create connections to the circuit,        2) build the electrical circuits on the wafer,        3) attach (bond with adhesive) the wafer to a carrier wafer with the circuits facing the carrier wafer, and        4) grind and etch the backside (called “blanket etch”) of the wafer to expose the copper interconnects.        
Each of these steps requires critical tolerances and process control. Four important measurements are identified as critical:                1) thickness of the wafer during and after the grind and blanket etch,        2) etch depth of the TSV,        3) surface height of the exposed copper interconnect, and        4) shape (i.e. warp, and bow) of the wafer.        
Semiconductor manufacturers measure wafer thickness for many reasons. For the 3DIC process described above, the wafer thickness is measured before bonding to a carrier, during the thinning process, and after the thinning process. In addition, the thicknesses of the adhesive layer and carrier wafer may also be required. The most common techniques for thinning a wafer are back grinding and etching, both of which operate on the back side, or non-device side, of the wafer. A manufacturer must polish or grind the back side of the wafer to the desired thickness with high uniformity. Tight monitoring of the wafer thickness, and thickness uniformity, is important in order to protect the TSVs. Too much thinning will damage the vias and ruin the circuits already constructed. Thinning too slowly reduces throughput and increases cost. Thinning in a non-uniform manner results in only some TSVs being properly exposed, thereby causing a low yield.
In addition to 3DICs, there are a variety of reasons why wafers need to be thinned. The most common are to improve heat dissipation, to improve the performance of image sensors, and to create Silicon On Insulator (SOI) type wafers. SOI is basically the fusing of two wafers with a thin oxide layer between the wafers. These wafers are commonly used for micro-electromechanical systems (MEMS) or for particular electronic properties of very thin silicon over a dielectric layer. The process typically involves attaching a device wafer to an oxide layer, frequently without an adhesive, and then polishing the device wafer to a specified thickness. The second wafer, which is known as the handle wafer, is sacrificial and is used simply to maintain the mechanical integrity of the device wafer.
There are many prior art methods for measuring wafer thickness. Examples are systems that utilize capacitive sensors, laser triangulation sensors, interferometers, and chromatic confocal sensors. Capacitive sensors require in-depth knowledge of the layer material and can generally only function correctly for a single layer of material, not wafer stacks. Additionally, capacitive sensors have a low thickness limit of approximately 200 microns, and are limited to a small sample of materials.
A technique using two opposing height sensors can measure thickness on thin samples and can accommodate multiple layers that are made of virtually any material, as they detect the physical surface of the wafer [4]. However, this technique requires delicate alignment in all three axes and requires calibration to “teach” the sensors how far apart they are in space. This calibration requirement is the lower limit to accuracy of the measurements made.
These systems fail when the wafer consists of multiple layers. The layers can include tape, a glass or silicon carrier, an adhesive layer, an insulator layer, and/or a product silicon layer. Because of the complicated structures and opacity to visible light of these various layers, the prior art systems might be able to measure the total thickness of an entire stack of layers, but rarely can they measure the thickness of the individual layers with high accuracy and repeatability.
Another type of prior art for wafer thickness measurement includes reflectometers and Fourier Transform Infrared (FTIR) spectrometer. For example, see [1, 6, 11, and 14]. These techniques measure thickness directly, and can usually differentiate between different layers, for example wafers bonded with an adhesive. However, these methods cannot measure shape as they produce no information regarding distance. Furthermore, when measuring multiple layers, these methods cannot determine the order of the layers. For example, if a sample consists of a thin silicon layer on top of a thick glass layer, reflectometer methods cannot determine whether the thin silicon layer is above or below the thick glass layer.
Specifically regarding the thinned wafers in the 3DIC process and the SOI process, there is no method of quickly and accurately measuring the thickness of a device wafer, other than the reflectometer described in [14]. Present technology measures the entire stack and cannot differentiate between the two wafers (device wafer and carrier wafer). Thus, process engineers are required to measure the carrier and the oxide layer prior to the attachment of the device wafer. These values are then subtracted from the total thickness measurement to produce the device layer thickness. In an alternative current method, wafers are thinned until visual inspection shows the vias exposed, with no knowledge of the thickness of the wafer.
For the measurement of narrow deep etches, whether round such as TSVs, or long such as trenches, optical non-contact techniques often fail when the aspect ratio (depth:width) of an etched feature is large and the width is small. The reason is because optical techniques cannot acquire information from the bottom of the etched feature when viewed from the top. This is true for confocal, interferometric, and other microscopic techniques. Optical techniques are limited to an aspect ratio of 2 or 3 to 1 when the feature width is approximately 5 μm or smaller. For trenches with a higher aspect ratio, the only current method to directly measure the depth is by destructively sectioning the wafer and viewing the trench from the side. Not only is the sample destroyed by this method, but electron microscopes are utilized, which are typically expensive and time consuming to use.
There are many prior art methods for measuring the depth of an etched feature on a wafer. Examples are systems that utilize white light interferometers, laser triangulation sensors, and chromatic confocal sensors [3]. All of these systems, that we are aware of, illuminate an etched feature from the top, i.e. the first surface to receive the illumination is the surface that is etched. In this configuration (“top illumination”) the ability of the system to measure the etched depth strongly depends on the aspect ratio of the etched feature. Aspect ratio is usually defined as the ratio of the etched feature depth to its width or diameter. When the width is small, but the depth large, very little of the source light is incident on the etched surface, which is located at the bottom of the trench or hole. At best, the measurement is made with low signal-to-noise ratio (SNR), and at worst there is no measurement at all.
Another prior art method that avoids some of the problems described above is Model-based infrared reflectometry (MBIR) [2]. MBIR is an indirect method that relies on the test object consisting of periodic structures. A large area of the test object is illuminated at a specific angle of incidence and then the reflected and diffracted fields are measured at different angles, wavelengths and polarizations. Dimensions of the test object, such as width and depth, are then calculated by solving an inverse physical model of the diffraction. MBIR is typically used to measure dimensions of small features, such as etched vias. However, it requires the presence of periodic structures and so cannot measure the etched depth of individual vias. Furthermore, MBIR cannot measure large scale shape, such as bow and warp, and MBIR cannot measure the thickness of multiple layers.
The measure of wafer shape, roughness, and exposed TSVs are inherently different from the thickness measurements described above. These parameters are measured as a distance to, or height of, a single specific surface. Both microscopic features, such as metal lines, and macroscopic measures, such as wafer warp, are included. In contrast, the thickness measurements described above relate to the distance between two surfaces. Thus, presently, different sensors or sensor arrangements are used for distance type measurements than for thickness type measurements.
Wafer warp and bow are industry standard metrics of wafer shape. Wafers typically warp as a result of coatings and adhesives being applied and processed at high temperature. As the wafer cools, the mismatch in thermal expansion of the different materials causes internal stress within the wafer, and thus bowing. Wafer shape is an important consideration for several reasons. Large warp prevents robotic wafer handlers from reliably loading wafers. As described above, wafers are typically bonded to carrier wafers as part of the 3DIC process, and a large warp and bow interfere with the bonding process. The problem becomes more severe as the wafers are thinned, as the internal stress within the wafer causes more bowing in a thin wafer than the same stress would in a thick wafer.
The height and height uniformity of the TSVs exposed by the thinning process disclosed above is important to the success of the 3DIC process. Other microscopic height profile measurements include surface roughness, the height of metal lines, the height of exposed TSV contacts, and the profile of micro-electromechanical features. One example of the prior art for distance or surface height measurement is a chromatic confocal height sensor [12].
Scanning White Light Interferometry, Low Coherence Interferometry, and Time Domain Optical Coherence Tomography are methods that typically employ broadband incoherent sources, such as a Michelson or Mirau interferometer, with the sample in one leg and a reference mirror in the other leg. The reference mirror is scanned in the axial direction to modulate the optical path difference (OPD) length between the two legs [7, 8]. Alternatively, the reference leg can be fixed and the measurement leg axially scanned.
The Low Coherence Interferometry microscope described by de Groot in [7] is not spectroscopic and requires axial scanning for each measurement. In essence, the spectroscopic nature of the present invention removes the axial scanning requirement of [7]. This prior art also describes the measurement of film thickness on a test object. However, the thickness measurement is not accomplished spectroscopically as in the present invention. De Groot measures film thickness by measuring spatial separation between axial fringes created during the axial scan. The present invention requires no axial scanning and measures film thickness through the analysis of the reflected spectrum.
Schwider [9] describes a white light interferometer arranged in a Fizeau configuration where the reference plate is 20 μm to 50 μm from the sample, and the reflected light is analyzed with a spectrometer. The air gap is the path length difference between the interfering waves, and so the periodicity shown in the spectrometer signal relates directly to the length of the air gap, and thus the height profile of the sample. The primary difficulty with this arrangement is a small working distance.
Frequency Domain Optical Coherence Tomography (also Fourier Domain OCT or FD-OCT) is an interferometric method where the sample reflects light in one leg of a Michelson interferometer, and the reference leg remains at a fixed position [10]. The source is broadband, and the spectrum of the light returned form the interferometer is analyzed in the Fourier domain. The OPD between the two legs causes fringes in the returned spectrum. FD-OCT systems can employ either an incoherent broadband source and a spectrometer as the detector, or a swept wavelength source with a photodiode detector and a data acquisition system.
Simultaneous Measurements and Microscope
For the measurement of wafer thickness and shape, present technology requires two separate sensors. One example of prior art uses one sensor that measures shape but not thickness, and a second sensor that measures thickness but not shape. If both sensors measure from the same side of the wafer, integration with a microscope becomes difficult. The addition of a microscope is desirable because it facilitates user interaction to determine precise measurement locations. Another example of prior art uses two shape sensors facing opposite sides of the wafer and a means of calibrating their separation. The ability to measure from a single side is desirable because it eliminates the need for a wafer chuck with an open bottom.
Another example of the utility of simultaneous thickness and distance measurements is a wafer having etched features that are followed by the deposition of a photoresist. The photoresist covers the whole wafer, including the bottom of the etched features. The measurements required for this wafer include etch depth, photoresist and wafer thicknesses, and wafer shape.
References
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